[Computer Architecture] Instructions : Language of the Computer

Instruction Set

• Arthmetic operation
• Logic operation
• Multiplication /Division
• Load from memory / Store to memory
• Jump / branch

Registers

RISC-V (RV32I) : 32 * 32 bit registers

32bit : Word
16bit : Half word
8bit : Byte

Register는 memory보다 빠름
Memory byte : 1byte (8-bit)

Memory에 있는 데이터를 바로 연산할 수 없다. load, compute, store의 단계를 거쳐야하므로, memory access를 줄이는 방향으로 가야한다.

Immediate Operands

The constant Zero

RISC-V register 0 (x0, 'zero') is the constant 0 (overwritten x)

Load Immediate Value

li : (pseudo-instruction)

Multiply

mul : lower 32 bits to
mulh : upper 32 bits to (signed numbers)
mulhu : upper 32 bits to (unsigned numbers)
mulhsu : upper 32 bits to (rs1 : signed, rs2: unsigned)

Unsigned Binary Integers

Using 32 bits: 0 ~ + 4294967295

Signed Binary Integers

2's Complement Signed Integers

1. negate all bits
2. add 1

-2^n-1 ~ 2^n-1 - 1
Using 32 bits: –2,147,483,648 to +2,147,483,647

Division

div : quotient
rem = remainder
divu / remu : unsigned versions

Logical Operations

And : 둘다 1일 때 1, 나머지는 0
Or : 1이 존재하면 1, 나머지는 그대로
Xor : 서로 다를 때 1, 같을 때 0
Not
: useful to invert bits in a word
a XORI -1 == Not a

Shift

types
Logical shift( unsigned)
Arithmetic( sigend) => retain sign bit

directiosn
left : mul by powers of 2
right : div by powers of 2

 

 

RV 32I Base Instruction Set

 

 

https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf